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d a t a sh eet preliminary speci?cation supersedes data of 1998 mar 27 file under integrated circuits, ic02 1998 oct 15 integrated circuits TDA8787 10-bit, 3.0 v analog-to-digital interface for ccd cameras
1998 oct 15 2 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 features correlated double sampling (cds), automatic gain control (agc), 10-bit analog-to-digital converter (adc) and reference regulator included fully programmable via a 3-wire serial interface sampling frequency up to 18 mhz agc gain range of 36 db (in steps of 0.1 db) low power consumption of only 190 mw (typ.) power consumption in standby mode of 4.5 mw (typ.) 3.0 v operation and 2.5 to 3.6 v operation for the digital outputs active control pulses polarity selectable via serial interface 8-bit dac included for analog settings ttl compatible inputs, cmos compatible outputs. applications low-power, low-voltage ccd camera systems. general description the TDA8787 is a 10-bit analog-to-digital interface for ccd cameras. the device includes a correlated double sampling circuit, agc and a low-power 10-bit adc together with its reference voltage regulator. agc gain is controlled via the serial interface. the adc input clamp level is controlled via the serial interface. an additional dac is provided for additional system controls; its output voltage range is 1.0 v (p-p) which is available at pin ofdout. quick reference data ordering information symbol parameter conditions min. typ. max. unit v cca analog supply voltage 2.7 3.0 3.6 v v ccd digital supply voltage 2.7 3.0 3.6 v v cco digital outputs supply voltage 2.5 2.6 3.6 v i cca analog supply current all clamps active - 55 70 ma i ccd digital supply current - 811ma i cco digital outputs supply current f pix = 18 mhz; c l =20pf; input ramp response time is 800 m s - 12ma adc res adc resolution - 10 - bits v i(cds)(p-p) maximum cds input voltage (peak-to-peak value) v cc = 2.85 v 650 -- mv v cc 3 3.0 v 800 -- mv f pix(max) maximum pixel rate 18 -- mhz f pix(min) minimum pixel rate 5 -- mhz dr agc agc dynamic range - 36 - db n tot(rms) total noise from cds input to adc output agc gain = 0 db; see fig.8 - 0.25 - lsb p tot total power consumption v cca =v ccd =v cco =3v - 190 - mw type number package name description version TDA8787hl lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2
1998 oct 15 3 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... block diagram fig.1 block diagram. o ok, full pagewidth mgm541 10-bit adc regulator cds clock generator pre- blanking output buffer 26 27 28 29 30 31 32 33 34 35 36 37 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ognd 25 v cco 44 dclpc 38 v ccd2 39 dgnd2 19 v ccd1 20 dgnd1 41 agnd3 42 v cca3 8 cpcds2 7 cpcds1 4 in 5 agnd1 9 ofdout 6 v cca1 oe 11 pbk 40 clk 43 agnd5 17 agnd2 2 dgnd3 1 v ccd3 18 v cca2 12 clpdm 13 clpob 47 shp shifter shift comparator correlated double sampling 7-bit register 9-bit register 8-bit register 46 45 oagc oagcc 16 15 14 3 test1 agnd4 test2 test3 48 shd serial interface 21 22 23 sen sclk sdata 24 vsync 10 stdby agc dac clamp v ref ofd dac data flip- flop clamp TDA8787
1998 oct 15 4 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 pinning symbol pin description v ccd3 1 digital supply voltage 3 dgnd3 2 digital ground 3 agnd4 3 analog ground 4 in 4 input signal from ccd agnd1 5 analog ground 1 v cca1 6 analog supply voltage 1 cpcds1 7 clamp storage capacitor pin 1 cpcds2 8 clamp storage capacitor pin 2 ofdout 9 analog output of the additional 8-bit control dac stdby 10 standby mode control input (low: TDA8787 active; high: TDA8787 standby) pbk 11 pre-blanking control input clpdm 12 clamp pulse input at dummy pixel clpob 13 clamp pulse input at optical black test1 14 test pin input 1 (should be connected to agnd2) test2 15 test pin input 2 (should be connected to agnd1) test3 16 test pin input 3 (should be connected to agnd2) agnd2 17 analog ground 2 v cca2 18 analog supply voltage 2 v ccd1 19 digital supply voltage 1 dgnd1 20 digital ground 1 sdata 21 serial data input for serial interface control sclk 22 serial clock input for serial interface sen 23 strobe pin for serial interface vsync 24 vertical sync pulse input v cco 25 output supply voltage ognd 26 digital output ground d0 27 adc digital output 0 (lsb) d1 28 adc digital output 1 d2 29 adc digital output 2 d3 30 adc digital output 3 d4 31 adc digital output 4 d5 32 adc digital output 5 d6 33 adc digital output 6 d7 34 adc digital output 7 d8 35 adc digital output 8 d9 36 adc digital output 9 (msb) oe 37 output enable control input (low: outputs active; high: outputs in high impedance) v ccd2 38 digital supply 2 dgnd2 39 digital ground 2 clk 40 data clock input
1998 oct 15 5 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 agnd3 41 analog ground 3 v cca3 42 analog supply 3 agnd5 43 analog ground 5 dclpc 44 regulator decoupling pin oagc 45 agc output (test pin) oagcc 46 agc complementary output (test pin) shp 47 preset sample-and-hold pulse input shd 48 data sample-and-hold pulse input symbol pin description fig.2 pin configuration. 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 12 24 37 25 TDA8787 mgm542 d9 d8 d7 d6 d4 d3 d2 d1 d0 ognd v cco v ccd3 dgnd3 agnd4 in agnd1 v cca1 cpcds2 ofdout pbk clpdm d5 shp oagcc oagc dclpc agnd5 v cca3 clk dgnd2 oe v ccd2 shd agnd3 cpcds1 stdby test1 test2 test3 agnd2 v cca2 v ccd1 dgnd1 sclk sen vsync clpob sdata
1998 oct 15 6 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. the supply voltages v cca , v ccd and v cco may have any value between - 0.3 and +7.0 v provided that the supply voltage difference d v cc remains as indicated. handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. thermal characteristics symbol parameter conditions min. max. unit v cca analog supply voltage note 1 - 0.3 +7.0 v v ccd digital supply voltage note 1 - 0.3 +7.0 v v cco output stages supply voltage note 1 - 0.3 +7.0 v d v cc supply voltage difference between v cca and v ccd - 1.0 +1.0 v between v cca and v cco - 1.0 +1.0 v between v ccd and v cco - 1.0 +1.0 v v i input voltage referenced to agnd - 0.3 +7.0 v i o data output current - 10 ma t stg storage temperature - 55 +150 c t amb operating ambient temperature - 20 +75 c t j junction temperature - 150 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 76 k/w
1998 oct 15 7 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 characteristics v cca =v ccd = 3.0 v; v cco = 2.6 v; f pix = 18 mhz; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v cca analog supply voltage 2.7 3.0 3.6 v v ccd digital supply voltage 2.7 3.0 3.6 v v cco digital outputs supply voltage 2.5 2.6 3.6 v i cca analog supply current all clamps active - 55 70 ma i ccd digital supply current - 811ma i cco digital outputs supply current c l = 20 pf on all data outputs; input ramp frequency - 12ma digital inputs i nputs : shp, shd, stdby, clpdm, clpob, sclk, sdata, sen, vsync, oe and pbk v il low-level input voltage 0 - 0.6 v v ih high-level input voltage 2.2 - v ccd v i i input current 0 v i v ccd - 2 - +2 m a clamps g lobal characteristics of the clamp loops t w(clamp) clamp active pulse width in number of pixels agc code = 383 for maximum 4 lsb error 18 -- pixels i nput clamp ( driven by clpdm) g m(cds) cds input clamp transconductance 1.5 2.7 3.5 ms o ptical black clamp ( driven by clpob) g shift gain from cpcds1 and 2 to agc inputs - 0.27 -- i lsb(cp) charge pump current for 1 lsb error at adc output agc code = 0 - 350 -m a agc code = 383 - 10 -m a i push(cp) available push current of the charge pump - 650 -m a i pull(cp) available pull current of the charge pump -- 650 -m a
1998 oct 15 8 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 correlated double sampling (cds) v i(cds)(p-p) maximum peak-to-peak cds input amplitude (video signal) v cc = 2.85 v 650 -- mv v cc 3 3.0 v 800 -- mv v reset(max) maximum cds input reset pulse amplitude 500 -- mv i i(in) input current into pin in (pin 4) at ?oating gate level - 1 - +1 m a t cds(min) cds control pulses minimum active time video input = v i(cds)(p-p) ; 2 lsb error at adc output 11 15 - ns t h(in-shp) cds input hold time (pin in) compared to control pulse shp v cca =v ccd =30v; t amb =25 c; see fig.9 35 7ns t h(in-shd) cds input hold time (pin in) compared to control pulse shd v cca =v ccd =30v; t amb =25 c; see fig.9 35 7ns ampli?er dr agc agc dynamic range - 36 - db d g agc maximum agc gain step - 0.3 - +0.3 db analog-to-digital converter (adc) le i integral linearity error f pix = 18 mhz; ramp input - 1.3 2.5 lsb le d differential linearity error f pix = 18 mhz; ramp input - 0.5 0.9 lsb total chain characteristics (cds + agc + adc) f pix(max) maximum pixel frequency 18 -- mhz t clkh clk pulse width high 15 -- ns t clkl clk pulse width low 15 -- ns t d(shd-clk) time delay between shd and clk see fig.9 10 -- ns t su(pbk-clk) set-up time of pbk compared to clk 10 -- ns v i(in) video input dynamic signal for adc full-scale output agc code = 00 800 -- mv agc code = 383 12.7 -- mv n tot(rms) total output noise (rms value) see fig.8 agc gai n=0db - 0.25 - lsb agc gai n=9db - 0.8 - lsb o ccd(max) maximum offset between ccd ?oating level and ccd dark pixel level - 70 - +70 mv v n(i)(eq)(rms) equivalent input noise voltage (rms value) - 110 -m v symbol parameter conditions min. typ. max. unit
1998 oct 15 9 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 digital-to-analog converter (ofdout dac) v ofdout(p-p) additional 8-bit control dac (ofd) output voltage (peak-to-peak value) r i =1m w- 1.0 - v v ofdout(0) dc output voltage for code 0 - agnd - v v ofdout(255) dc output voltage for code 255 - agnd + 1.0 - v tc dac dac output range temperature coef?cient - 250 - ppm/ c z ofdout dac output impedance - 2000 -w i ofdout ofd output current drive static -- 100 m a digital outputs (f pix = 18 mhz; c l =22pf) v oh high-level output voltage i oh = - 1ma v cco - 0.5 - v cco v v ol low-level output voltage i ol = 1 ma 0 - 0.5 v i oz output current in 3-state mode 0.5v 1998 oct 15 10 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 fig.3 pixel frequency timing diagram; all polarities active high. handbook, full pagewidth n 0.6 v 2.2 v n + 1n + 2n + 3 t cds(min) t clkh t h(in-shp) 0.6 v 0.6 v 0.6 v 0.6 v t h(in-shd) 0.6 v 2.2 v 2.2 v t cds(min) t d(shd-clk) t su(pbk-clk) 2.2 v mgm764 in shp shd clk sdata pbk t h(o) t d(o) n - 1 n 50%
1998 oct 15 11 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 fig.4 pixel frequency timing diagram; all polarities active low. handbook, full pagewidth n 2.2 v 2.2 v n + 1n + 2n + 3 t cds(min) t clkl t h(in-shp) 0.6 v 0.6 v 0.6 v t h(in-shd) 0.6 v 2.2 v t cds(min) t d(shd-clk) t su(pbk-clk) 2.2 v 2.2 v 2.2 v fce088 in shp shd clk sdata pbk t h(o) t d(o) n - 1 n 50% fig.5 dac voltage output as a function of dac input code. handbook, full pagewidth mgm543 0 ofdout dac voltage output (v) 1.0 0 255 ofdout control dac input code
1998 oct 15 12 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 (1) in case the number of clamp pixels is limited to 18t w(clamp) ; otherwise this timing interval can be smaller. (2) when dummy pixels are not available. fig.6 line frequency timing diagram. handbook, full pagewidth mgm544 clpdm (active high) pbk (active high) clpob (active high) agcout 4 pixels (1) video optical black clpob window horizontal flyback dummy video pbk window 4 pixels (1) clpdm window (2) fig.7 agc gain as a function of agc input code. handbook, halfpage 0 64 192 320 agc input code 128 agc gain (db) 256 384 42 30 6 - 6 0 12 24 36 18 fce057
1998 oct 15 13 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 fig.8 total noise performance as a function of agc gain. noise measurement at adc outputs: coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. front-end works at 18 mpixels with line of 1024 pixels whose first 40 are used to run clpob and the last 40 for clpdm. data at the adc outputs are measured during the other pixels. as a result of this, the standard deviation of the codes statistic is computed, resulting in the noise. no quantization noise is taken into account as no signal is inputted. handbook, halfpage 64 0 192 320 128 agc code 256 383 fce098 n tot(rms) (lsb) 10 8 6 4 2 0
1998 oct 15 14 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 fig.9 serial interface block diagram. handbook, full pagewidth ofdout dac latches agc gain latches adc clamp latches control pulse polarity latches latch selection d0 lsb msb s data sclk sen 8-bit dac mgm546 agc control adc clamp control control pulses polarity settings d1 d2 d3 d4 d5 10 d6 shift register d7 d8 d9 a0 a1 8 9 7 6 fig.10 loading sequence of control input data via the serial interface. t su1 =t su2 =t su3 = 10 ns (min.); t hd3 =t hd4 = 10 ns (min.). handbook, full pagewidth mgm547 sdata sclk sen a1 a0 d9 d7 d6 d5 d4 d3 msb lsb d2 d1 d0 t hd3 t su3 t su1 t hd4 t su2 d8
1998 oct 15 15 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 table 1 serial interface programming table 2 polarity settings note 1. bit d4 is not used. table 3 standby selection address bits data bits d9 to d0 a1 a0 0 0 agc gain control (d8 to d0); bit d9 should be set to logic 0 0 1 dac ofdout output control (d7 to d0); bits d8 and d9 should be set to logic 0 1 0 adc clamp reference control (d6 to d0); bits d7, d8 and d9 should be set to logic 0 1 1 control pulses (pins shp, shd, clpdm, clpob, pbk and clk) polarity settings symbol pin serial control bit (1) active edge or level shp and shd 47 and 48 d0 1 = high; 0 = low clk 40 d1 1 = rising; 0 = falling clpdm 12 d2 1 = high; 0 = low clpob 13 d3 1 = high; 0 = low pbk 11 d5 1 = high; 0 = low vsync 24 d6 0 = rising; 1 = falling stdby adc digital outputs d9 to d0 i cca +i cco +i ccd (typ.) 1 logic state low 1 ma 0 active 64 ma
1998 oct 15 16 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 application diagram fig.11 application diagram. (1) pins sen and vsync should be interconnected when vertical sync signal is not available. (2) input signals in, shd and shp must be adjusted to comply with timing signals t h(in-shp) and t h(in-shd) (see chapter characteristics). handbook, full pagewidth mgm548 1 2 3 4 5 6 7 8 9 10 11 36 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 35 34 33 32 31 30 29 28 27 26 12 25 TDA8787hl d9 d8 d7 d6 d4 d3 d2 d1 d0 ognd v cco v ccd3 dgnd3 agnd4 in agnd1 v cca1 cpcds2 ofdout pbk clpdm d5 shp oagcc oagc dclpc agnd5 v cca3 clk dgnd2 oe v ccd2 shd agnd3 cpcds1 stdby test1 test2 test3 agnd2 v cca2 v ccd1 dgnd1 sclk sen vsync clpob sdata serial interface v cca v ccd ccd (2) v ccd v ccd v ccd v cca 100 nf v ccd 100 nf v ccd 100 nf 100 nf 100 nf v cca 100 nf 1 m f 1 m f 1 m f 1 m f 1 m f (1) (2) (2)
1998 oct 15 17 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 94-12-19 97-08-01 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
1998 oct 15 18 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all lqfp packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. wave soldering wave soldering is not recommended for lqfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. caution wave soldering is not applicable for all lqfp packages with a pitch (e) equal or less than 0.5 mm. if wave soldering cannot be avoided, for lqfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 oct 15 19 philips semiconductors preliminary speci?cation 10-bit, 3.0 v analog-to-digital interface for ccd cameras TDA8787 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
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communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 545104/750/02/pp20 date of release: 1998 oct 15 document order number: 9397 750 04259

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